Geometric control of diffusing elements on InAs semiconductor surfaces via metal contacts.

Local geometric control of basic synthesis parameters, such as elemental composition, is important for bottom-up synthesis and top-down device definition on-chip but remains a significant challenge. Here, we propose to use lithographically defined metal stacks for regulating the surface concentrations of freely diffusing synthesis elements on compound semiconductors. This is demonstrated by geometric control of Indium droplet formation on Indium Arsenide surfaces, an important consequence of incongruent evaporation. Lithographic defined Aluminium/Palladium metal patterns induce well-defined droplet-free zones during annealing up to 600 °C, while the metal patterns retain their lateral geometry. Compositional and structural analysis is performed, as well as theoretical modelling. The Pd acts as a sink for free In atoms, lowering their surface concentration locally and inhibiting droplet formation. Al acts as a diffusion barrier altering Pd's efficiency. The behaviour depends only on a few basic assumptions and should be applicable to lithography-epitaxial manufacturing processes of compound semiconductors in general.

Reconfigurable signal modulation in a ferroelectric tunnel field-effect transistor.

Reconfigurable transistors are an emerging device technology adding new functionalities while lowering the circuit architecture complexity. However, most investigations focus on digital applications. Here, we demonstrate a single vertical nanowire ferroelectric tunnel field-effect transistor (ferro-TFET) that can modulate an input signal with diverse modes including signal transmission, phase shift, frequency doubling, and mixing with significant suppression of undesired harmonics for reconfigurable analogue applications. We realize this by a heterostructure design in which a gate/source overlapped channel enables nearly perfect parabolic transfer characteristics with robust negative transconductance. By using a ferroelectric gate oxide, our ferro-TFET is non-volatilely reconfigurable, enabling various modes of signal modulation. The ferro-TFET shows merits of reconfigurability, reduced footprint, and low supply voltage for signal modulation. This work provides the possibility for monolithic integration of both steep-slope TFETs and reconfigurable ferro-TFETs towards high-density, energy-efficient, and multifunctional digital/analogue hybrid circuits.

Effects of Interface Oxidation on Noise Properties and Performance in III-V Vertical Nanowire Memristors.

Memristors implemented as resistive random-access memories (RRAMs) owing to their low power consumption, scalability, and speed are promising candidates for in-memory computing and neuromorphic applications. Moreover, a vertical 3D implementation of RRAMs enables high-density crossbar arrays at a minimal footprint. Co-integrated III-V vertical gate-all-around MOSFET selectors in a one-transistor-one-resistor (1T1R) configuration have recently been demonstrated where an interlayer (IL)-oxide has been shown to enable high RRAM endurance needed for applications like machine learning. In this work, we evaluate the role of the IL-oxide directly on InAs vertical nanowires using low-frequency noise characterization. We show that the low-frequency noise or the 1/f-noise in InAs vertical RRAMs can be reduced by more than 3 orders of magnitude by engineering the InAs/high-k interface. We also report that the noise properties of the vertical 1T1R do not degrade significantly after RRAM integration making them attractive to be used in emerging electronic circuits.

Sensing single domains and individual defects in scaled ferroelectrics.

Ultra-scaled ferroelectrics are desirable for high-density nonvolatile memories and neuromorphic computing; however, for advanced applications, single domain dynamics and defect behavior need to be understood at scaled geometries. Here, we demonstrate the integration of a ferroelectric gate stack on a heterostructure tunnel field-effect transistor (TFET) with subthermionic operation. On the basis of the ultrashort effective channel created by the band-to-band tunneling process, the localized potential variations induced by single domains and individual defects are sensed without physical gate-length scaling required for conventional transistors. We electrically measure abrupt threshold voltage shifts and quantify the appearance of new individual defects activated by the ferroelectric switching. Our results show that ferroelectric films can be integrated on heterostructure devices and indicate that the intrinsic electrostatic control within ferroelectric TFETs provides the opportunity for ultrasensitive scale-free detection of single domains and defects in ultra-scaled ferroelectrics. Our approach opens a previously unidentified path for investigating the ultimate scaling limits of ferroelectronics.

Correction: Strain mapping inside an individual processed vertical nanowire transistor using scanning X-ray nanodiffraction.

Correction for 'Strain mapping inside an individual processed vertical nanowire transistor using scanning X-ray nanodiffraction' by Dmitry Dzhigaev et al., Nanoscale, 2020, 12, 14487-14493, DOI: 10.1039/D0NR02260H.

Improved Electrostatics through Digital Etch Schemes in Vertical GaSb Nanowire p-MOSFETs on Si.

Sb-based semiconductors are critical p-channel materials for III-V complementary metal oxide semiconductor (CMOS) technology, while the performance of Sb-based metal-oxide-semiconductor field-effect transistors (MOSFETs) is typically inhibited by the low quality of the channel to gate dielectric interface, which leads to poor gate modulation. In this study, we achieve improved electrostatics of vertical GaSb nanowire p-channel MOSFETs by employing robust digital etch (DE) schemes, prior to high-κ deposition. Two different processes, based on buffer-oxide etcher (BOE) 30:1 and HCl:IPA 1:10, are compared. We demonstrate that water-based BOE 30:1, which is a common etchant in Si-based CMOS process, gives an equally controllable etching for GaSb nanowires compared to alcohol-based HCl:IPA, thereby realizing III-V on Si with the same etchant selection. Both DE chemicals show good interface quality of GaSb with a substantial reduction in Sb oxides for both etchants while the HCl:IPA resulted in a stronger reduction in the Ga oxides, as determined by X-ray photoelectron spectroscopy and in agreement with the electrical characterization. By implementing these DE schemes into vertical GaSb nanowire MOSFETs, a subthreshold swing of 107 mV/dec is obtained in the HCl:IPA pretreated sample, which is state of the art compared to reported Sb-based MOSFETs, suggesting a potential of Sb-based p-type devices for all-III-V CMOS technologies.

Ferroelectric-Antiferroelectric Transition of Hf1-x Zr x O2 on Indium Arsenide with Enhanced Ferroelectric Characteristics for Hf0.2Zr0.8O2.

The ferroelectric (FE)-antiferroelectric (AFE) transition in Hf1-x Zr x O2 (HZO) is for the first time shown in a metal-ferroelectric-semiconductor (MFS) stack based on the III-V material InAs. As InAs displays excellent electron mobility and a narrow band gap, the integration of ferroelectric thin films for nonvolatile operations is highly relevant for future electronic devices and motivates further research on ferroelectric integration. When increasing the Zr fraction x from 0.5 to 1, the stack permittivity increases as expected, and the transition from FE to AFE-like behavior is observed by polarization and current-voltage characteristics. At x = 0.8 the polarization of the InAs-based stacks shows a larger FE-contribution as a more open hysteresis compared to both literature and reference metal-ferroelectric-metal (MFM) devices. By field-cycling the devices, the switching domains are studied as a function of the cycle number, showing that the difference in FE-AFE contributions for MFM and MFS devices is stable over switching and not an effect of wake-up. The FE contribution of the switching can be accessed by successively lowering the bias voltage in a proposed pulse train. The possibility of enhanced nonvolatility in Zr-rich HZO is relevant for device stacks that would benefit from an increase in permittivity and a lower operating voltage. Additionally, an interfacial layer (IL) is introduced between the HZO film and the InAs substrate. The interfacial quality is investigated as frequency-dependent capacitive dispersion, showing little change for varying ZrO2 concentrations and with or without included IL. This suggests material processing that is independently limiting the interfacial quality. Improved endurance of the InAs-Hf1-x Zr x O2 devices with x = 0.8 was also observed compared to x = 0.5, with further improvement with the additional IL for Zr-rich HZO on InAs.

Performance enhancement of GaSb vertical nanowire p-type MOSFETs on Si by rapid thermal annealing.

GaSb is considered as an attractive p-type channel material for future III-V metal-oxide-semiconductor (MOS) technologies, but the processing conditions to utilize the full device potential such as low power logic applications and RF applications still need attention. In this work, applying rapid thermal annealing (RTA) to nanoscale GaSb vertical nanowire p-type MOS field-effect transistors, we have improved the average peak transconductance (gm,peak) by 50% among 28 devices and achieved 70µSµm-1atVDS = -0.5 V in a device with 200 nm gate length. In addition, a low subthreshold swing down to 144 mV dec-1as well as an off-current below 5 nAµm-1which refers to the off-current specification in low-operation-power condition has been obtained. Based on the statistical analysis, the results show a great enhancement in both on- and off-state performance with respect to previous work mainly due to the improved electrostatics and contacts after RTA, leading to a potential in low-power logic applications. We have also examined a short channel device withLg = 80 nm in RTA, which shows an increasedgm,peakup to 149µSµm-1atVDS = -0.5 V as well as a low on-resistance of 4.7 kΩ·µm. The potential of further enhancement ingmvia RTA offers a good alternative to obtain high-performance devices for RF applications which have less stringent requirement for off-state performance. Our results indicate that post-fabrication annealing provides a great option to improve the performance of GaSb-based p-type devices with different structures for various applications.

Doping Profiles in Ultrathin Vertical VLS-Grown InAs Nanowire MOSFETs with High Performance.

Thin vertical nanowires based on III-V compound semiconductors are viable candidates as channel material in metal oxide semiconductor field effect transistors (MOSFETs) due to attractive carrier transport properties. However, for improved performance in terms of current density as well as contact resistance, adequate characterization techniques for resolving doping distribution within thin vertical nanowires are required. We present a novel method of axially probing the doping profile by systematically changing the gate position, at a constant gate length L g of 50 nm and a channel diameter of 12 nm, along a vertical nanowire MOSFET and utilizing the variations in threshold voltage V T shift (∼100 mV). The method is further validated using the well-established technique of electron holography to verify the presence of the doping profile. Combined, device and material characterizations allow us to in-depth study the origin of the threshold voltage variability typically present for metal organic chemical vapor deposition (MOCVD)-grown III-V nanowire devices.

Strain mapping inside an individual processed vertical nanowire transistor using scanning X-ray nanodiffraction.

Semiconductor nanowires in wrapped, gate-all-around transistor geometry are highly favorable for future electronics. The advanced nanodevice processing results in strain due to the deposited dielectric and metal layers surrounding the nanowires, significantly affecting their performance. Therefore, non-destructive nanoscale characterization of complete devices is of utmost importance due to the small feature sizes and three-dimensional buried structure. Direct strain mapping inside heterostructured GaSb-InAs nanowire tunnel field-effect transistor embedded in dielectric HfO2, W metal gate layers, and an organic spacer is performed using fast scanning X-ray nanodiffraction. The effect of 10 nm W gate on a single embedded nanowire with segment diameters down to 40 nm is retrieved. The tensile strain values reach 0.26% in the p-type GaSb segment of the transistor. Supported by the finite element method simulation, we establish a connection between the Ar pressure used during the W layer deposition and the nanowire strain state. Thus, we can benchmark our models for further improvements in device engineering. Our study indicates, how the significant increase in X-ray brightness at 4th generation synchrotron, makes high-throughput measurements on realistic nanoelectronic devices viable.

Nanowire Tunnel FET with Simultaneously Reduced Subthermionic Subthreshold Swing and Off-Current due to Negative Capacitance and Voltage Pinning Effects.

Nanowire tunnel field-effect transistors (TFETs) have been proposed as the most advanced one-dimensional (1D) devices that break the thermionic 60 mV/decade of the subthreshold swing (SS) of metal oxide semiconductor field-effect transistors (MOSFETs) by using quantum mechanical band-to-band tunneling and excellent electrostatic control. Meanwhile, negative capacitance (NC) of ferroelectrics has been proposed as a promising performance booster of MOSFETs to bypass the aforementioned fundamental limit by exploiting the differential amplification of the gate voltage under certain conditions. We combine these two principles into a single structure, a negative capacitance heterostructure TFET, and experimentally demonstrate a double beneficial effect: (i) a super-steep SS value down to 10 mV/decade and an extended low slope region that is due to the NC effect and, (ii) a remarkable off-current reduction that is experimentally observed and explained for the first time by the effect of the ferroelectric dipoles, which set the surface potential in a slightly negative value and further blocks the source tunneling current in the off-state. State-of-the-art InAs/InGaAsSb/GaSb nanowire TFETs are employed as the baseline transistor and PZT and silicon-doped HfO2 as ferroelectric materials.

Feature size control using surface reconstruction temperature in block copolymer lithography for InAs nanowire growth.

Here we present a method to control the size of the openings in hexagonally organized BCP thin films of poly(styrene)-block-poly(4-vinylpyridine) (PS-b-P4VP) by using surface reconstruction. The surface reconstruction is based on selective swelling of the P4VP block in ethanol, and its extraction to the surface of the film, resulting in pores upon drying. We found that the BCP pore diameter increases with ethanol immersion temperature. In our case, the temperature range 18 to 60 °C allowed fine-tuning of the pore size between 14 and 22 nm. A conclusion is that even though the molecular weight of the respective polymer blocks is fixed, the PS-b-P4VP pore diameter can be tuned by controlling temperature during surface reconstruction. These results can be used for BCP-based nanofabrication in general, and for vertical nanowire growth in particular, where high pattern density and diameter control are of importance. Finally, we demonstrate successful growth of indium arsenide InAs vertical nanowires by selective-area metal-organic vapor phase epitaxy (MOVPE), using a silicon nitride mask patterned by the proposed PS-b-P4VP surface reconstruction lithography method.

Impact of source doping on the performance of vertical InAs/InGaAsSb/GaSb nanowire tunneling field-effect transistors.

In this paper, we analyze experimental data from state-of-the-art vertical InAs/InGaAsSb/GaSb nanowire tunneling field-effect transistors (TFETs) to study the influence of source doping on their performance. Overall, the doping level impacts both the off-state and on-state performance of these devices. Separation of the doping from the heterostructure improved the subthreshold swing of the devices. The best devices reached a point subthreshold swing of 30 mV/dec at 100 x higher currents than previous Si-based TFETs. However, separation of doping from the heterostructure had a significant impact on the on-state performance of these devices due to effects related to source depletion. An increase in the doping level helped to improve the on-state performance, which also increased the subthreshold swing. Thus, further optimization of doping incorporation with the heterostructure will help to improve vertical InAs/InGaAsSb/GaSb nanowire TFETs.

Vertical InAs/InGaAs Heterostructure Metal-Oxide-Semiconductor Field-Effect Transistors on Si.

III-V compound semiconductors offer a path to continue Moore's law due to their excellent electron transport properties. One major challenge, integrating III-V's on Si, can be addressed by using vapor-liquid-solid grown vertical nanowires. InAs is an attractive material due to its superior mobility, although InAs metal-oxide-semiconductor field-effect transistors (MOSFETs) typically suffer from band-to-band tunneling caused by its narrow band gap, which increases the off-current and therefore the power consumption. In this work, we present vertical heterostructure InAs/InGaAs nanowire MOSFETs with low off-currents provided by the wider band gap material on the drain side suppressing band-to-band tunneling. We demonstrate vertical III-V MOSFETs achieving off-current below 1 nA/µm while still maintaining on-performance comparable to InAs MOSFETs; therefore, this approach opens a path to address not only high-performance applications but also Internet-of-Things applications that require low off-state current levels.

Individual Defects in InAs/InGaAsSb/GaSb Nanowire Tunnel Field-Effect Transistors Operating below 60 mV/decade.

Tunneling field-effect transistors (TunnelFET), a leading steep-slope transistor candidate, is still plagued by defect response, and there is a large discrepancy between measured and simulated device performance. In this work, highly scaled InAs/InxGa1-xAsySb1-y/GaSb vertical nanowire TunnelFET with ability to operate well below 60 mV/decade at technically relevant currents are fabricated and characterized. The structure, composition, and strain is characterized using transmission electron microscopy with emphasis on the heterojunction. Using Technology Computer Aided Design (TCAD) simulations and Random Telegraph Signal (RTS) noise measurements, effects of different type of defects are studied. The study reveals that the bulk defects have the largest impact on the performance of these devices, although for these highly scaled devices interaction with even few oxide defects can have large impact on the performance. Understanding the contribution by individual defects, as outlined in this letter, is essential to verify the fundamental physics of device operation, and thus imperative for taking the III-V TunnelFETs to the next level.

Low Trap Density in InAs/High-k Nanowire Gate Stacks with Optimized Growth and Doping Conditions.

In this paper, we correlate the growth of InAs nanowires with the detailed interface trap density (Dit) profile of the vertical wrap-gated InAs/high-k nanowire semiconductor-dielectric gate stack. We also perform the first detailed characterization and optimization of the influence of the in situ doping supplied during the nanowire epitaxial growth on the sequential transistor gate stack quality. Results show that the intrinsic nanowire channels have a significant reduction in Dit as compared to planar references. It is also found that introducing tetraethyltin (TESn) doping during nanowire growth severely degrades the Dit profile. By adopting a high temperature, low V/III ratio tailored growth scheme, the influence of doping is minimized. Finally, characterization using a unique frequency behavior of the nanowire capacitance-voltage (C-V) characteristics reveals a change of the dopant incorporation mechanism as the growth condition is changed.

Low Leakage-Current InAsSb Nanowire Photodetectors on Silicon.

Axially doped p-i-n InAs0.93Sb0.07 nanowire arrays have been grown on Si substrates and fabricated into photodetectors for shortwave infrared detection. The devices exhibit a leakage current density around 2 mA/cm(2) and a 20% cutoff of 2.3 µm at 300 K. This record low leakage current density for InAsSb based devices demonstrates the suitability of nanowires for the integration of III-V semiconductors with silicon technology.

III-V Nanowire Complementary Metal-Oxide Semiconductor Transistors Monolithically Integrated on Si.

III-V semiconductors have attractive transport properties suitable for low-power, high-speed complementary metal-oxide-semiconductor (CMOS) implementation, but major challenges related to cointegration of III-V n- and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) on low-cost Si substrates have so far hindered their use for large scale logic circuits. By using a novel approach to grow both InAs and InAs/GaSb vertical nanowires of equal length simultaneously in one single growth step, we here demonstrate n- and p-type III-V MOSFETs monolithically integrated on a Si substrate with high I(on)/I(off) ratios using a dual channel, single gate-stack design processed simultaneously for both types of transistors. In addition, we demonstrate fundamental CMOS logic gates, such as inverters and NAND gates, which illustrate the viability of our approach for large scale III-V MOSFET circuits on Si.

Quantized Conduction and High Mobility in Selectively Grown In(x)Ga(1-x)As Nanowires.

We report measured quantized conductance and quasi-ballistic transport in selectively regrown In0.85Ga0.15As nanowires. Very low parasitic resistances obtained by regrowth techniques allow us to probe the near-intrinsic electrical properties, and we observe several quantized conductance steps at 10 K. We extract a mean free path of 180 ± 40 nm and an effective electron mobility of 3300 ± 300 cm(2)/V·s, both at room temperature, which are among the largest reported values for nanowires of similar dimensions. In addition, optical characterization of the nanowires by photoluminescence and Raman measurement is performed. We find an unintentional increase of indium in the InxGa1-xAs composition relative to the regrown film layer, as well as partial strain relaxation.

InAs nanowire MOSFETs in three-transistor configurations: single balanced RF down-conversion mixers.

Integration of III-V semiconductors on Si substrates allows for the realization of high-performance, low power III-V electronics on the Si-platform. In this work, we demonstrate the implementation of single balanced down-conversion mixer circuits, fabricated using vertically aligned InAs nanowire devices on Si. A thin, highly doped InAs buffer layer has been introduced to reduce the access resistance and serve as a bottom electrode. Low-frequency voltage conversion gain is measured up to 7 dB for a supply voltage of 1.5V. Operation of these mixers extends into the GHz regime with a -3 dB cut-off frequency of 2 GHz, limited by the optical lithography system used. The circuit dc power consumption is measured at 3.9 mW.